The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. This fabrication technique may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.
Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, an amorphous silicon (a-Si) or polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
For improving low off-state leakage current, due to the fundamentally superior short channel control characteristics, ETSOI and FinFET are the best candidates for complementary metal-oxide-semiconductors (CMOS) beyond the 22 nm node. As illustrated in FIG. 1, an ETSOI semiconductor device begins with an ETSOI substrate comprising a silicon substrate 101, a buried oxide layer 103, and a thin silicon layer 105. A gate electrode 107 (including, from top to bottom, silicon nitride (SiN) cap 109, a-Si layer 111, and gate oxide layer 113) is patterned on the silicon layer of the ETSOI substrate. The silicon layer thickness is typically between about 6 nm and about 8 nm.
Adverting to FIG. 2A, during the patterning of gate electrode 107, the region 201 immediately adjacent to gate 107 is eroded by about 1 nm by the overetch process needed to insure that no gate-stack residual is left in the non-gated area. Then, in defining spacers 203, illustrated in FIG. 2B, the ETSOI is further thinned by about 1 to about 2 nm from the spacer etch/strip/clean steps, i.e., when the resist is stripped post halo extension implants. This causes very thin “bottle-neck” ETSOI extension regions 205 that have a high extension resistance (Rext) that is a few times higher than a conventional SOI or bulk CMOS.
An approach to mitigate the high ETSOI Rext is to form a raised source/drain 207 on the ETSOI by an epitaxial growth process. However, since the raised source/drain epitaxial growth does not change the silicon thickness at the thinnest portion of the extension, under the spacers 203 that separate the gate electrode from the source/drain epitaxial growth, the “bottle-neck” region cannot be remedied merely by forming raised source/drain 207. Rext is still dominated by the extension region resistance. High Rext limits the application of ETSOI to low power applications. In order to enable ETSOI for high performance logic devices, the Rext must be significantly reduced.
A need therefore exists for methodology enabling the formation of an SOI semiconductor device which is compatible with high-k metal gate integration and which has low off-state leakage current and reduced Rext, and for the resulting device.